FIG. 1 is a schematic structural diagram of a dual-loop phase-locked loop circuit. The dual-loop phase-locked loop circuit includes a phase frequency detector, a charge pump, a loop low-pass filter, a first voltage-current conversion unit, a second voltage-current conversion unit, a current-controlled oscillator, and a frequency divider. The loop low-pass filter includes a first filter unit and a second filter unit, where a circuit that includes a resistor R1 and a capacitor C1 in the first filter unit has a relatively large time constant, and the time constant is far greater than a time constant of a circuit that includes a resistor R2 and a capacitor C2 in the second filter unit. Compared with the second voltage-current conversion unit, the first voltage-current conversion unit has a relatively large voltage-current conversion gain. The first voltage-current conversion unit and the first filter unit form a coarse adjustment circuit, which is configured to coarsely adjust a frequency of a phase-locked loop output signal to approach a target frequency. The second voltage-current conversion unit and the second filter unit form a fine adjustment circuit, which is configured to finely adjust a frequency of a phase-locked loop output signal to a target frequency. The current-controlled oscillator is configured to generate a phase-locked loop output signal whose frequency is a target frequency. The frequency divider is configured to divide a frequency of a phase-locked loop output signal. The time constant of the circuit that includes the resistor R1 and the capacitor C1 in the first filter unit is relatively large, which results in a long locking time for the dual-loop phase-locked loop circuit and a low response speed.